The present invention relates generally to data processors to be connected to a data bus and, more particularly, to a memory competition circuit for avoiding competition among requests for access to the memory of a data processor.
FIG. 7 shows a plurality of conventional data processors 1 connected to a bus 2. Each data processor 1 includes a central processing unit (CPU) 3 for performing arithmetic operation and control to process data, a memory 4 for storing information necessary to process data, a receiver buffer 5 for temporarily storing a received packet, a transmitter buffer 6 for temporarily storing a packet to be transmitted, a bus control circuit 7 for controlling the transmission and reception of a packet from the bus 2, a driver/receiver 8 for receiving or transmitting a packet to the bus 2, a gate circuit 9 for controlling communications between the receiver buffer 5 and the CPU 3, and a gate circuit 10 for controlling communications between the transmitter buffer 6 and the CPU 3.
In operation, for purposes of simplicity, it is assumed that all data is transmitted in units of byte. The data processor 1 takes in a packet addressed to it from the bus 2. After processing, it transmits a response packet to a predetermined data processor. Since packets are transmitted at random from other data processors, the data processor 1 needs to finish the above processing cycle--reception, data processing, and transmission to the bus--as soon as possible. The CPU 3 of the data processor 1 executes the above process according to a program stored in the memory 4.
The receiver buffer 5 and transmitter buffer 6 are made of high-speed memories capable of transmitting data at high speeds and temporarily store a packet received from or transmitted to the bus 2. The bus control circuit 7 controls the transmission and reception of a packet from the bus 2. When the data processor 1 does not engage in transmission or reception of data from the bus 2, it is put in a state always able to receive data from the bus 2. At this point, the gate circuit 9 is closed, and the receiver buffer 5 receives a packet from the bus 2 independently of the operation of the CPU 3. The gate circuit 10 may be closed or opened.
In FIG. 8, when the bus control circuit 7 finds a packet addressed to it on the bus 2 (Step S1), it transfers the packet to the receiver buffer 5 via the driver/receiver 8 (Step S2). Upon completion of the packet reception (Step S3), the bus control circuit 7 is put in a busy state to inhibit reception of the next packet (Step S4). The CPU 3 opens the gate circuit 9, interprets the contents of the received packet, and performs a process specified by the contents (Step S5). Upon completion of the process, the CPU 3 closes the gate circuit 9 and releases the bus control circuit 7 from the busy state so as to enable the next reception from the bus 2 (Step S6).
The CPU 3 then opens the gate circuit 10 and prepares a response packet for the transmission buffer 6 (Step S7). Upon completion of preparation of the response packet, the CPU 3 closes the gate circuit 10 and instructs the bus control circuit 7 for transmission (Step S8). The bus control circuit 7 occupies the bus 2 with an access method inherent to the system and transmits the contents of the transmitter buffer 6 to the bus 2 via the driver/receiver 8 (Step S9).
The steps S5-S8 involve a job portion processed by the CPU 3 according to the program, and the steps S1-S4 and step S9 are for job portions processed by the other hardware. The steps S1-S4 and S5-S8 are carried out in parallel, and the steps S5-S8 and S9 are carried out in parallel.
In the conventional data processor as described above, the next packet is unable to be received until the process of a received packet is completed. Consequently, the transmitting data processor needs a device for repeating the transmission of a packet until the receiving data processor takes it. When the receiving unit takes much time to process, the contents of a received packet must be moved to a work area of the memory 4 to empty the receiver buffer. It is also necessary to provide separate transmitter and receiver buffers. Particularly, the frequency of busy states in the receiver buffer becomes so high that it lowers the efficiency of the processor.